1. Field of the Invention
This invention relates to a MOS field effect transistor which operates at high speed and with low power consumption. The layers for a source region and a drain region are deposited by molecular layer epitaxial growth at temperatures of 850 degree centigrade (.degree.C.) or less by which the thickness of the layer can be controlled with a degree of accuracy on the order of a single atom layer. In addition, a lightly doped region and a heavily doped region are provided at least in the drain region, which forms a lightly doped drain (LDD) structure, during the molecular layer epitaxial growth. The combination of the molecular layer epitaxial growth and the LDD structure according to the invention enables to reduce an overlap of the gate over each of the source region and drain region to 500.ANG. or less resulting in higher operation speed and low power consumption.
2. Prior art
Miniaturization technique is indispensable for improving the efficiency and performance of semiconductor devices. However, one of the problems in miniaturizing an insulated gate field effect transistor (MOS FET) with an extremely short channel length is the short channel effect in which threshold voltage is lowered. This is caused by the shortened effective channel length as a result of spreading of depletion region toward the gate from a drain region. In order to prevent the short channel effect, the following measures are provided : (i) to increase impurity concentration in channel region; and (ii) to decrease the thickness of the source/drain diffusion layers and to decrease their horizontal extension of diffusion toward the gate. In the light of the above, a MOS EFT having LDD structure has conventionally been provided according to the process shown in FIG. 2(a)-(e). After the surface oxidization of, for example, p-type substrate 7, a polysilicon layer is deposited and a gate 9 is formed by using a photo resist 10, as shown in FIG. 2 (a) and (b). In FIG. 2(c), n- ion implantation and thereafter annealing (generally at 1000.degree.-1200.degree. C.) are carried out to form lightly doped regions 11 and 12. At this stage thermal diffusion occurs towards the region under the gate. FIG. 2 (d) shows a step in which after the photo resist 10 is removed, a mask film 15 for ion implantation is deposited by chemical vapor deposition (CVD), and n+ ion implantation is carried out to form n+regions 13 and 14. The mask film 15 damaged by the ion implantation is removed and then an oxide film 16 is deposited as shown in FIG. 2(e).
However, the conventional measure as described hereabove are not fully satisfactory. Since the impurity implantation is carried out by ion implantation and then annealing is carried out generally at 1000.degree.-1200.degree. C., three dimensional diffusion defined by the ion acceleration energy and annealing temperature can not be avoided, and consequently there are limitations in terms of the control of diffusion depth. It was therefore extremely difficult or almost impossible to control diffusion depth with a degree of accuracy on the order of 1000 .ANG. or less.